`timescale 1ns / 1ps

`include "MIPSCPU_COMMON.vh"

module Processor(
	rst,
	clk_100M_in,
	cpu_enable,
	out_reg_zero_value,
	out_reg_t0_value,
	out_reg_t1_value,
	out_reg_t2_value,
	out_reg_t3_value,
	out_reg_ra_value
    );

	input rst, clk_100M_in, cpu_enable;
	wire clk_100M, clk_50M, clk_25M, clk_12M5, clk_6M25, clk_3M125;
	output wire[`DATA_WIDTH - 1 : 0] out_reg_zero_value, out_reg_t0_value, out_reg_t1_value, out_reg_t2_value, out_reg_t3_value, out_reg_ra_value;
	
	IPCoreClock clocks_i
    (
		.clk_in(clk_100M_in),
		.clk_100M(clk_100M),
		.clk_50M(clk_50M),
		.clk_25M(clk_25M),
		.clk_12M5(clk_12M5),
		.clk_6M25(clk_6M25),
		.clk_3M125(clk_3M125)
	);
	
	wire[`DATA_WIDTH - 1 : 0] pc_value;
	wire[`DATA_WIDTH - 1 : 0] instr;
	
	CPUMain cpu_i
	(
		.rst(rst),
		.clk_100M(clk_100M),
		.clk_25M(clk_25M),
		.cpu_enable(cpu_enable),
		.instr(instr),
		.out_pc_value(pc_value),
		.out_reg_zero_value(out_reg_zero_value),
		.out_reg_t0_value(out_reg_t0_value),
		.out_reg_t1_value(out_reg_t1_value),
		.out_reg_t2_value(out_reg_t2_value),
		.out_reg_t3_value(out_reg_t3_value),
		.out_reg_ra_value(out_reg_ra_value)
	);
	
	TempROM temp_rom_i
	(
		.instr_addr(pc_value),
		.instr(instr)
	);
	
endmodule
